8-bit serial-in parallel-out shift register 74F164
FEATURES
• Gated serial data inputs
• Typical shift frequency of 100MHz
• Asynchronous Master Reset
• Buffered clock and data inputs
• Fully synchronous data transfer
• Industrial temperature range available (–40 to +85 °C)
DESCRIPTION
The 74F164 is an 8-bit edge-triggered shift register with serial data
entry and an output from each of the eight stages. Data is entered
through one of two inputs (Dsa, Dsb); either input can be used as an
active High enable for data entry through the other input. Both inputs
must be connected together or an unused input must be tied High.
Data shifts one place to the right on each Low-to-High transition of
the clock (CP) input, and enters into Q0 the logical AND of the two
data inputs (Dsa, Dsb) that existed one setup time before the rising
edge. A Low level on the Master Reset (MR) input overrides all
other inputs and clears the register asynchronously, forcing all
outputs Low.
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