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74F169 (DIP)
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4-bit up/down binary synchronous counter 74F169

FEATURES
• Synchronous counting and loading
• Up/Down counting
• Modulo 16 binary counter
• Two Count Enable inputs for n-bit cascading
• Positive edge-triggered clock
• Built-in carry look-ahead capability
• Presettable for programmable operation

DESCRIPTION
The 74F169 is a 4-bit synchronous, presettable Modulo 16 up/down
counter featuring an internal carry look-ahead for applications in
high-speed counting designs. Synchronous operation is provided by
having all flip-flops clocked simultaneously so that the outputs
change coincident with each other when instructed by the Count
Enable inputs and internal gating. This mode of operation eliminates
the output spikes which are normally associated with asynchronous
(ripple clock) counters. A buffered clock input triggers the flip-flops
on the Low-to-High transition of the clock.
The counter is fully programmable; that is, the outputs may be
preset to either level.
Presetting is synchronous with the clock and takes place regardless
of the levels of the Count Enable inputs. A Low level on the Parallel
Enable (PE) input disables the counter and causes the data at the
Dn input to be loaded into the counter on the next Low-to-High
transition of the clock.
The direction of counting is controlled by the Up/Down (U/D) input; a
High will cause the count to increase, a Low will cause the count to
decrease.
The carry look-ahead circuitry provides for n-bit synchronous
applications without additional gating. Instrumental in accomplishing
this function are two Count Enable inputs (CET, CEP) and a
Terminal Count (TC) output. Both Count Enable inputs must be Low
to count. The CET input is fed forward to enable the TC output. The
TC output thus enabled will produce a Low output pulse with a
duration approximately equal to the High level portion of the Q0
output. The Low level TC pulse is used to enable successive
cascaded stages.


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