Latch/flip-flop 74F573/74F574
74F573 Octal Transparent Latch (3-State)
74F574 Octal D Flip-Flop (3-State)
FEATURES
• 74F573 is broadside pinout version of 74F373
• 74F574 is broadside pinout version of 74F374
• Inputs and Outputs on opposite side of package allow easy
interface to Microprocessors
• Useful as an Input or Output port for Microprocessors
• 3-State Outputs for Bus interfacing
• Common Output Enable
• 74F563 and 74F564 are inverting version of 74F573 and 74F574
respectively
• 3-State Outputs glitch free during power-up and power-down
• These are High-Speed replacements for N8TS805 and N8TS806
DESCRIPTION
The 74F573 is an octal transparent latch coupled to eight 3-State
output buffers. The two sections of the device are controlled
independently by Enable (E) and Output Enable (OE) control gates.
The 74F573 is functionally identical to the 74F373 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
The data on the D inputs is transferred to the latch outputs when the
Enable (E) input is High. The latch remains transparent to the data
input while E is High and stores the data that is present one setup
time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independent to the latch operation. When OE is Low, the latched or
transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
The 74F574 is functionally identical to the 74F374 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocesors.
It is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by the clock (CP) and Output Enable (OE) control gates.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independently of the latch operation. When OE is Low, the latched
or transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
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