3-to-8 line decoder/demultiplexer; inverting 74LVC138A
FEATURES
• Wide supply voltage range of 1.2 to 3.6 V
• In accordance with JEDEC standard no. 8-1A
• Inputs accept voltages up to 5.5 V
• CMOS lower power consumption
• Direct interface with TTL levels
• Demultiplexing capability
• Multiple input enable for easy expansion
• Ideal for memory chip select decoding
• Active LOW mutually exclusive outputs
• Output drive capability 50 transmission lines at 85°C
DESCRIPTION
The 74LVC138A is a low-voltage, low-power, high-performance
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
The 74LVC138A accepts three binary weighted address inputs (A0,
A1, A2) and when enabled, provides 8 mutually exclusive active
LOW outputs (Y0 to Y7).
The 74LVC138A features three enable inputs: two active LOW (E1
and E2) and one active HIGH (E3). Every output will be HIGH unless
E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the
74LV138A to a 1-of-32 (5 lines to 32 lines) decoder with just four
74LV138A ICs and one inverter. The 74LV138A can be used as an
eight output demultiplexer by using one of the active LOW enable
inputs as the data input and the remaining enable inputs as strobes.
Unused enable inputs must be permanently tied to their appropriate
active HIGH or LOW state.
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