Single inverter 74LVC1G04
FEATURES
· Wide supply voltage range from 1.65 to 5.5 V
· High noise immunity
· Complies with JEDEC standard:
– JESD8-7 (1.65 to 1.95 V)
– JESD8-5 (2.3 to 2.7 V)
– JESD8B/JESD36 (2.7 to 3.6 V).
· ±24 mA output drive (VCC = 3.0 V)
· CMOS low power consumption
· Latch-up performance £250 mA
· Direct interface with TTL levels
· Inputs accept voltages up to 5 V
· Multiple package options
· Specified from -40 to +125 °C.
DESCRIPTION
The 74LVC1G04 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Input can be driven from either 3.3 or 5 V devices. These
features allow the use of these devices in a mixed
3.3 and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant
for slower input rise and fall time.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC1G04 provides the inverting buffer.
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