Dual D-type flip-flop with set and reset; positive-edge trigger
FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interface with TTL levels • Output drive capability 50 transmission lines @ 85¡ÆC
DESCRIPTION The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC74A is a dual positive edge triggered, D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action in all data inputs makes the circuit highly tolerant to slower clock rise and fall times.
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