Hex D-type flip-flop with reset; positive edge-trigger 74LV174
FEATURES
• Wide operating voltage: 1.0 to 5.5V
• Optimized for Low Voltage applications: 1.0 to 3.6V
• Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
• Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V,
Tamb = 25°C
• Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V,
Tamb = 25°C
• Output capability: standard
• ICC category: MSI
DESCRIPTION
The 74LV174 is a low–voltage Si–gate CMOS device and is pin and
function compatible with the 74HC/HCT174.
The 74LV174 has six edge–triggered D–type flip–flops with
individual D inputs and Q outputs. The common clock (CP) and
master reset (MR) inputs load and reset (clear) all flip–flops
simultaneously.
The register is fully edge–triggered. The state of each D input, one
set–up time prior to the LOW–to–HIGH clock transition, is
transferred to the corresponding output of the flip–flop.
A LOW level on the MR input forces all outputs LOW, independently
of clock or data inputs.
The device is useful for applications requiring true outputs only and
clock and master reset inputs that are common to all storage
elements.
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