Octal D-type transparent latch (3-State) 74LV373
FEATURES
• Wide operating voltage: 1.0 to 5.5V
• Optimized for Low Voltage applications: 1.0V to 3.6V
• Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
• Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V,
Tamb = 25°C
• Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V,
Tamb = 25°C
• Common 3-State output enable input
• Output capability: bus driver
• ICC category: MSI
DESCRIPTION
The 74LV373 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT373.
The 74LV373 is an octal D-type transparent latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. A latch enable (LE) input and an output enable (OE)
input are common to all internal latches.
The ‘373’ consists of eight D-type transparent latches with 3-State
true outputs. When LE is HIGH, data at the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a latch
output will change each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
The ‘373’ is functionally identical to the ‘573’, but the ‘573’ has a
different pin arrangement.
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