8-bit static shift register
DESCRIPTION
The HEF4021B is an 8-bit static shift register
(parallel-to-serial converter) with a synchronous serial
data input (DS), a clock input (CP), an asynchronous active
HIGH parallel load input (PL), eight asynchronous parallel
data inputs (P0 to P7) and buffered parallel outputs from
the last three stages (05 to O7).
Each register stage is a D-type master-slave flip-flop with
a set direct/clear direct input. Information on P0 to P7 is
asynchronously loaded into the register while PL is HIGH,
independent of CP and DS. When PL is LOW, data on
DS is shifted into the first register position and all the data
in the register is shifted one position to the right on the
LOW to HIGH transition of CP. Schmitt-trigger action in the
clock input makes the circuit highly tolerant to slower clock
rise and fall times.
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