Untitled Document
 
Untitled Document
 
ºñ¹Ð¹øÈ£ È®ÀÎ ´Ý±â
 
IC > ·ÎÁ÷ IC > CMOS4000(SMD) > HEF4017BT (SO16)
ÃÖ¼ÒÁÖ¹®¼ö·® : 50°³
HEF4017BT (SO16)
ÃÖ¼ÒÁÖ¹®¼ö·® : 50°³
Á¦Á¶È¸»ç : ANY
ÆǸŰ¡°Ý : 490¿ø
Àû¸³±Ý¾× : 0¿ø
¼ö·®  : °³
¡Ú¡Ú¡Ú¡Ú¡Ú
½Å¼ÓÇÏ°í Á¤È®ÇÑ ¹è¼ÛÀ» ¾à¼Óµå¸³´Ï´Ù
  
 

5-stage Johnson counter

DESCRIPTION
The HEF4017B is a 5-stage Johnson decade counter with
ten spike-free decoded active HIGH outputs (Oo to O9), an
active LOW output from the most significant flip-flop (O5-9),
active HIGH and active LOW clock inputs (CP0, CP1) and
an overriding asynchronous master reset input (MR).
The counter is advanced by either a LOW to HIGH
transition at CP0 while CP1 is LOW or a HIGH to LOW
transition at CP1 while CP0 is HIGH (see also function
table).
When cascading counters, the O5-9 output, which is LOW
while the counter is in states 5, 6, 7, 8 and 9, can be used
to drive the CP0 input of the next counter.
A HIGH on MR resets the counter to zero
(Oo = O5-9 = HIGH; O1 to O9 = LOW) independent of the
clock inputs (CP0, CP1).
Automatic code correction of the counter is provided by an
internal circuit: following any illegal code the counter
returns to a proper counting mode within 11 clock pulses.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.


µ¥ÀÌÅͽÃÆ® º¸±â


* º» Á¦Ç°Àº °æ¿ì¿¡ µû¶ó ȣȯµÇ´Â Å¸»ç Á¦Ç°À¸·Î º¯°æµÉ ¼ö ÀÖÀ½À» ¾Ë·Á µå¸³´Ï´Ù.

  ÁÖ¹®½Ã Âü°í Çϼ¼¿ä~~

* Á¦Ç° »ç¿ë Àü ¹Ýµå½Ã Å×½ºÆ® ÈÄ »ç¿ëÇϽñ⠹ٶø´Ï´Ù.
* Ã·ºÎµÈ µ¥ÀÌÅͽÃÆ®´Â Âü°í¿ëÀ¸·Î¸¸ »ç¿ëÇϽñ⠹ٶø´Ï´Ù.

   
À̸§ :
³»¿ë :
ÆòÁ¡
 
 
 
 
¹øÈ£ Á¦¸ñ ÀÛ¼ºÀÚ ÀÛ¼ºÀÏ Á¶È¸
 
 

Untitled Document