Dual 4-bit static shift register
DESCRIPTION
The HEF4015B is a dual edge-triggered 4-bit static shift
register (serial-to-parallel converter). Each shift register
has a serial data input (D), a clock input (CP), four fully
buffered parallel outputs (O0 to O3) and an overriding
asynchronous master reset input (MR). Information
present on D is shifted to the first register position, and all
the data in the register is shifted one position to the right
on the LOW-to-HIGH transition of CP. A HIGH on MR
clears the register and forces O0 to O3 to LOW,
independent of CP and D. Schmitt-trigger action in the
clock input makes the circuit highly tolerant to slower clock
rise and fall times.
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