8-bit static shift register
DESCRIPTION
The HEF4014B is a fully synchronous edge-triggered 8-bit
static shift register with eight synchronous parallel inputs
(P0 to P7), a synchronous serial data input (DS), a
synchronous parallel enable input (PE), a LOW to HIGH
edge-triggered clock input (CP) and buffered parallel
outputs from the last three stages (O5 to O7).
Operation is synchronous and the device is edge-triggered
on the LOW to HIGH transition of CP. Each register stage
is of a D-type master-slave flip-flop. When PE is HIGH,
data is loaded into the register from P0 to P7 on the LOW
to HIGH transition of CP. When PE is LOW, data is shifted
to the first position from DS, and all the data in the register
is shifted one position to the right on the LOW to HIGH
transition of CP. Schmitt-trigger action in the clock input
makes the circuit highly tolerant to slower clock rise and
fall times
데이터시트 보기
* 본 제품은 경우에 따라 호환되는 타사 제품으로 변경될 수 있음을 알려 드립니다.
주문시 참고 하세요~~
|
