8-Bit Serial In/Parallel Out Shift Register
General Description
These 8-bit shift registers feature gated serial inputs and
an asynchronous clear. A low logic level at either input
inhibits entry of the new data, and resets the first flip-flop to
the low level at the next clock pulse, thus providing complete
control over incoming data. A high logic level on
either input enables the other input, which will then determine
the state of the first flip-flop. Data at the serial inputs
may be changed while the clock is HIGH or LOW, but only
information meeting the setup and hold time requirements
will be entered. Clocking occurs on the LOW-to-HIGH level
transition of the clock input. All inputs are diode-clamped to
minimize transmission-line effects.
Features
Gated (enable/disable) serial inputs
Fully buffered clock and serial inputs
Asynchronous clear
Typical clock frequency 36 MHz
Typical power dissipation 80 mW
데이터시트 보기
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