DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54 /74LS113A offers individual J, K, set, and clock inputs. These
monolithic dual flip-flops are designed so that when the clock goes HIGH, the
inputs are enabled and data will be accepted. The logic level of the J and K
inputs may be allowed to change when the clock pulse is HIGH and the
bistable will perform according to the truth table as long as minimum setup
times are observed. Input data is transferred to the outputs on the
negative-going edge of the clock pulse.
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