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74LS154 (DIP)
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4-Line to 16-Line Decoder/Demultiplexer

General Description
Each of these 4-line-to-16-line decoders utilizes TTL circuitry
to decode four binary-coded inputs into one of sixteen
mutually exclusive outputs when both the strobe
inputs, G1 and G2, are LOW. The demultiplexing function
is performed by using the 4 input lines to address the output
line, passing data from one of the strobe inputs with the
other strobe input LOW. When either strobe input is HIGH,
all outputs are HIGH. These demultiplexers are ideally
suited for implementing high-performance memory decoders.
All inputs are buffered and input clamping diodes are
provided to minimize transmission-line effects and thereby
simplify system design.

Features
 Decodes 4 binary-coded inputs into one of 16 mutually
  exclusive outputs
 Performs the demultiplexing function by distributing data
  from one input line to any one of 16 outputs
 Input clamping diodes simplify system design
 High fan-out, low-impedance, totem-pole outputs
 Typical propagation delay
 - 3 levels of logic 23 ns
 - Strobe 19 ns
 Typical power dissipation 45 mW


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