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EPM3032ATC44-10 ÃÖ¼ÒÁÖ¹®¼ö·® : 10°³ |
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Á¦Á¶È¸»ç : ALTERA |
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Features ¡á High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX¢ç architecture (see Table 1) ¡á 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – ISP circuitry compliant with IEEE Std. 1532 ¡á Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 ¡á Enhanced ISP features: – Enhanced ISP algorithm for faster programming – ISP_Done bit to ensure complete programming – Pull-up resistor on I/O pins during in–system programming ¡á High–density PLDs ranging from 600 to 10,000 usable gates ¡á 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz ¡á MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels ¡á Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGATM packages ¡á Hot–socketing support ¡á Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance ¡á Industrial temperature range
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